Abstract

The adoption of novel AI hardware is often hindered by the lack of available deployment solutions. To address this challenge, multi-target deep learning (DL) compilers have emerged, offering a large variety of optimizations and automated deployment solutions that bridge the gap between AI software and hardware. However, support for dedicated AI accelerators remains limited due to their vast architectural differences and unique characteristics.This paper introduces a novel compiler-aware AI hardware design for edge devices that improves the deployment of AI workloads on edge AI accelerators by aligning the hardware architecture with the capabilities of DL compilers. By analyzing workload representations in the DL compiler TVM, we derive architecture-level and component-level design principles to enhance accelerator usability. We demonstrate this approach with a programmable edge AI accelerator, optimized through a compiler-driven design space exploration and implemented in GlobalFoundries 22FDX+, achieving an energy efficiency of 0.697 pJ/MAC for EEG-based seizure detection and video capsule endoscopy.